HDI High-Density Interconnect — Detailed Explanation of Any-Layer Interconnect (ELIC) Technology

ELIC (Every Layer Interconnect) is an advanced core process for high-end HDI (High-Density Interconnect) PCBs. Unlike traditional HDI, which relies on fixed build-up sequences and suffers from limited interlayer connectivity, ELIC completely eliminates internal mechanical through-holes and buried vias, using only laser-drilled microvias to enable direct electrical connections between any two layers of the board—thereby breaking through the hierarchical barriers inherent in 1st-, 2nd-, and 3rd-order HDI structures. As a key enabling technology for ultra-high-density routing and high-speed, high-frequency signal transmission, ELIC has been widely adopted in high-end precision electronics.

1. Core Differences Between Traditional HDI and ELIC

Traditional sequential-build HDI is constrained by a "core + fixed build-up" structure, imposing strict hierarchical limitations on interlayer connectivity and restricting both routing flexibility and density. In contrast, ELIC employs a full additive build-up architecture that enables barrier-free interlayer connections. The key differences are summarized in the table below:

2. Core Technical Features of ELIC

ELIC achieves comprehensive upgrades across multiple dimensions—including stack-up design, material systems, microvia fabrication, and routing strategies—to establish a high-density, high-speed, and highly reliable technical framework.

1. Barrier-Free Full Additive Stack-Up Design

ELIC abandons the traditional passive "fixed core + external build-up" approach and instead adopts a fully additive process involving sequential lamination, layer-by-layer laser drilling, and stepwise patterning. For example, in a 10-layer ELIC board, all adjacent layers from L1 to L10 are interconnected via high-precision laser microvias, eliminating core constraints and hierarchical connectivity barriers. This allows flexible stack-up planning tailored to product requirements, meeting demands for high layer counts and ultra-fine routing.

2. Low-Loss, Ultra-Thin Advanced Material System

To support ultra-high-density routing and high-speed, high-frequency signal transmission, ELIC utilizes low-loss, ultra-thin base and auxiliary materials to minimize signal loss and enhance routing accuracy at the source:

Dielectric Layers: Employ 50–100μm ultra-thin prepreg (PP) combined with high-end substrates featuring low Dk and low dissipation factor, effectively reducing dielectric loss and signal delay in high-frequency transmission and ensuring signal integrity.

Conductive Layers: Use 12–18μm ultra-thin copper foil (1/3 oz to 1/2 oz), enabling ultra-fine line fabrication and supporting mass production with line/space widths as small as ≤50μm.

3. High-Precision Laser Microvia Process Specifications

All interlayer connections in ELIC are formed using UV/CO₂ laser drilling. Compared to traditional mechanical drilling, this method achieves smaller vias, higher precision, and significantly improved space utilization. Key process parameters are as follows:

4. High-Density Routing and BGA Fan-Out Optimization Strategy

By completely eliminating internal mechanical buried vias, ELIC frees up large internal routing areas, making it ideally suited for ultra-fine-pitch packages such as 0.3mm BGA. Component pads can be vertically fanned out to lower layers via dedicated one-to-one laser microvias, eliminating the need for surface routing or additional transition vias and fundamentally avoiding surface trace interference.

Moreover, the any-layer direct-connect architecture entirely removes stubs caused by traditional vias, significantly reducing signal loss, crosstalk, and reflections in high-speed transmission—thus optimizing signal integrity for high-frequency, high-speed applications.

5. Standardized Stack-Up and Electrical Network Planning

ELIC uses a coreless, integrated stack-up structure composed of "all-PP dielectric + ultra-thin copper foil." A typical layer sequence is: L1 (signal) – PP dielectric – L2 (signal/power) – PP dielectric – … – Ln (signal), offering flexible and unconstrained layer arrangement.

Electrical network planning follows high-speed and stability principles: power and ground networks are centralized on inner layers to ensure stable power delivery and robust grounding; high-speed signals are prioritized on outer and near-outer layers, with interlayer transitions strictly adhering to the shortest-path rule to minimize signal attenuation and delay.

6. Ultra-Fine Routing Parameter Standards

Leveraging precision materials and laser micromachining, ELIC enables ultra-high-accuracy circuit fabrication. Key mass-production specifications include: minimum line/space width of 40/40μm and impedance tolerance controlled within ±10%, meeting stringent impedance-matching requirements for high-end precision circuits.

3. ELIC Manufacturing Process and Quality Control Standards

1. Core Process Flow

ELIC employs a closed-loop, sequential additive build-up process with a standardized workflow: single-layer lamination → precision laser microvia drilling → electroplating and via filling → curing, repeated bidirectionally until the full board is formed. End-to-end closed-loop control ensures consistent lamination accuracy, drilling quality, and plating performance across all layers, guaranteeing stable and uniform interlayer connectivity.

2. Interlayer Alignment Accuracy Standards

High-precision alignment is fundamental to ELIC. Stringent mass-production standards require: overall interlayer registration error ≤ ±25μm and stacked via vertical offset ≤ 15μm, effectively preventing misalignment, via shift, short circuits, and other process defects.

3. Laser Microvia Filling Quality Standards

All laser microvias must be 100% fully filled with electroplated copper, featuring smooth, flat surfaces with no dents, bumps, or pinholes. Internally, vias must be free of voids, gaps, or contaminants to prevent long-term failures such as oxidation, open circuits, or abnormal resistance, ensuring long-term reliability.

4. Key DFM Pre-Verification Checkpoints

A complete DFM (Design for Manufacturability) review must be conducted prior to mass production, focusing on critical parameters including interlayer alignment, plating/filling quality, annular ring width, via pitch, line/space width, and impedance. This proactively identifies and resolves design-process conflicts, stabilizes yield, and ensures both electrical performance and structural reliability.

4. Application Scenarios and Cost Characteristics

1. Key Application Scenarios

Thanks to its ultra-high routing density, exceptional high-speed signal integrity, and superior structural reliability, ELIC is primarily used in high-end, compact, high-speed, and high-frequency electronic devices. Typical applications include:

Flagship smartphones and foldable phone motherboards

High-end CPU/GPU advanced package substrates

5G/6G base station high-frequency PCBs

High-speed servers and cloud computing motherboards

Military radar and aerospace high-frequency communication PCBs

2. Cost Characteristics

ELIC incurs relatively high costs, primarily due to expensive ultra-thin advanced materials, significant investment in precision laser microvia equipment, complex sequential build-up processes, and extremely stringent process control requirements. For the same layer count, an ELIC any-layer interconnect PCB costs more than twice that of a conventional high-end HDI board. Furthermore, as layer count and process complexity increase, the cost premium becomes even more pronounced—making ELIC a quintessential "high-performance, high-cost" advanced PCB technology.

5. Comprehensive Comparison of Mainstream HDI Technologies

To clearly differentiate the application suitability and performance characteristics of various HDI technologies, the following comparison evaluates 1st-order HDI, 2nd-order HDI, and ELIC across multiple dimensions including structure, interconnect capability, performance, and cost:

ELIC any-layer interconnect technology overcomes the structural and process limitations of traditional sequential-build HDI. Through its innovative architecture—featuring all-laser microvias, zero mechanical holes, and full additive build-up—it achieves maximum interlayer connectivity freedom and the highest possible routing density. It also fundamentally enhances high-speed signal transmission performance, making it ideally suited for cutting-edge applications such as 5G high-frequency communications, AI hardware, high-performance computing, and advanced packaging that demand ultra-high density, speed, and reliability. However, due to its process complexity and high cost, product designers and manufacturers must carefully balance performance requirements against budget constraints when selecting this technology to achieve optimal cost-performance trade-offs.