TSMC's target price raised! AI-driven advanced process capacity surges

　　
　　Amid surging AI chip demand, TSMC receives another major boost! On March 9, Morgan Stanley released a research report raising TSMC’s ([2330.TW](2330.TW)) target price to NT$2,288 (from NT$2,088) and increasing ASE Group’s ([3711.TW](3711.TW)) target price to NT$368 (from NT$338), maintaining an “Overweight” rating for both companies. The report noted that TSMC is accelerating expansion of its advanced process and packaging capacity, with capital expenditures projected to reach USD 65 billion in 2027 and USD 70 billion in 2028, driven primarily by AI-related business which will continue fueling rapid revenue growth.


I. Key Highlights:

Increased Capital Expenditure Accelerates Capacity Expansion
1. Significantly higher capex, exceeding prior expectations
Driven by soaring AI chip demand, TSMC’s capacity expansion is far more aggressive than previously anticipated:
• 2027 capital expenditure raised to USD 65 billion (from USD 59 billion), further increasing to USD 70 billion in 2028 (from USD 60 billion), primarily allocated to building advanced-node fabs (3nm/2nm) and advanced packaging capacity;
• Improved ramp-up efficiency: the entire cycle—from cleanroom construction to equipment installation and mass production of new nodes—has been shortened by nine months compared to five years ago: cleanroom construction reduced from 18 to 15 months, equipment installation from 8 to 6 months, and node ramp-up from 16 to 12 months.

2. Advanced-node capacity surge; 3nm/2nm become core growth drivers
• 3nm capacity: global monthly capacity expected to reach 160,000 wafers by 2026 (including 50,000 wafers from Kumamoto, Japan), growing to 180,000–190,000 wafers/month by 2028, primarily serving NVIDIA Rubin and Google TPU v7 AI chips;
• 2nm/1.6nm capacity: nearly 100,000 wafers/month by end-2026, rising to 155,000 wafers/month in 2027 and reaching 195,000 wafers/month in 2028, serving clients including AMD, Apple, Qualcomm, and AI ASIC vendors;
• Next-generation nodes: 1.4nm equipment installation to begin in 2027, with mass production scaling up in 2028;
1.0nm expected to enter limited production at the Tainan fab in 2029.

3. Advanced packaging expands in parallel; CoWoS capacity doubles
TSMC continues advancing its “Foundry 2.0” strategy, with advanced packaging becoming a key growth engine:
• CoWoS capacity: to reach 120,000 wafers/month by end-2026, expanding further to 165,000 wafers/month by end-2027, while outsourcing part of CoWoS interposer production to Vanguard International Semiconductor (VIS) using 55/65nm processes,
contributing an estimated 50,000 wafers/month capacity in 2027;
• Other packaging technologies: SoIC (System on Integrated Chips) capacity to reach 14,000 wafers/month by end-2026, doubling to 28,000 wafers/month in 2027, primarily for AMD GPUs and Apple data center chips;
• Overseas packaging footprint: an advanced packaging R&D and manufacturing center to be built in Arizona, USA, with equipment installation starting in second half 2027 and mass production beginning in 2028.


II. Financial Performance & Business Outlook: AI Becomes Primary Growth Engine, Driving Revenue and Margins Higher

AI business share surges, becoming core revenue pillar
• Revenue contribution: AI-related revenue already reached high teens in 2025, projected to exceed 30% in 2026 and rise above 40% by 2029;
• Growth momentum: AI semiconductor-related revenue CAGR (compound annual growth rate) from 2024 to 2029 estimated at 60%, with AI chip foundry revenue reaching USD 116 billion in 2029—accounting for 43% of TSMC’s total revenue;
• Demand sources: 3nm/2nm orders from AI chip leaders like NVIDIA, Google, and AMD, plus advanced-node demand for AI server CPUs and networking chips.

ASE benefits in tandem: capturing outsourced packaging demand from TSMC
As TSMC’s key advanced packaging partner, ASE Group continues benefiting from spillover AI packaging demand:
• Earnings upgrades: EPS forecasts for 2026–2028 raised by 1%, 2%, and 9% respectively; advanced packaging/testing revenue projected to reach USD 5.5 billion in 2027, representing 15–20% of total revenue;
• Capacity expansion: accelerating CoWoS and other advanced packaging capacity build-outs, with simultaneous progress on equipment installation and facility construction, positioning ASE for high-growth revenue post-2027.

III. Industry Impact & Risk Considerations

1. Industry landscape: mature-node capacity spillover benefits second-tier players
As TSMC focuses on advanced nodes, mature-node (28nm and above) capacity is spilling over:
• Beneficiaries: second-tier foundries like VIS, UMC, and Powerchip will absorb some mature-node orders; rising demand for PMICs and memory-related chips is also driving wafer price increases (e.g., Powerchip raised logic chip prices by 10–15% in 1H26);
• Competitive edge: TSMC maintains a solid lead in 3nm/2nm technology, with high dependency from global AI chip giants; 3nm utilization expected to approach 100% in 2026, and 2nm utilization to rapidly climb to full capacity in 2027.

2. Key risks
• Downside risks: weaker-than-expected AI chip demand;
cost overruns in overseas fab construction;
increased competition if Intel or Samsung achieve breakthroughs in advanced nodes;
sluggish consumer electronics demand dragging down mature-node utilization;
• Upside opportunities: stronger-than-expected AI server demand accelerating 3nm/2nm capacity fill rates;
increased CPU foundry orders from Intel;
new applications like 6G driving additional advanced-node demand.

Discussion Time:
Do you think TSMC’s USD 65 billion capex plan for 2027 will be fully realized? Will 3nm/2nm capacity remain fully utilized through 2028? Besides ASE, which other packaging vendors could capture TSMC’s spillover demand?

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